Title: Optimal reliable constraints-based design space exploration in VLSI for power grid design

Authors: Praveen Andrew; Vinay Kumar Sadolalu Boregowda

Addresses: Department of Electronics Engineering, JAIN (Deemed-to-be University), Bengaluru, Karnataka 562112, India ' Electronics and Communication Engineering, JAIN (Deemed-to-be University), Bengaluru, Karnataka 562112, India

Abstract: The task of developing a power grid network (PGN) for a VLSI device is challenging because of the increase in network complexity. The PGN's metallic line resistances result in voltage dips called IR drops, which can change the voltage level of simple logic circuits and lead to system-on-chip (SoC) malfunction. Numerous reliability restrictions also have an impact on the IR drop, and breaking any of those rules might make the IR drop considerably worse. Hence, as it does not require any modifications to the grid's structure, the implementation of longer wires is proposed here. Consequently, the process of minimising inductive radiation drop is automated, and as such, the objectives encompass area, voltage drop, and penalty. Additionally, a new optimisation crisis is measured for dependability limitations, and the elephant herding updated whale algorithm (EHU-WA), a combination of the whale optimisation (WOA) and elephant herding optimisation (EHO) algorithms, is developed to solve this.

Keywords: VLSI; IR drop; wire length; voltage drop; EHU-WA algorithm.

DOI: 10.1504/IJPELEC.2025.144695

International Journal of Power Electronics, 2025 Vol.21 No.2, pp.97 - 128

Received: 30 Oct 2023
Accepted: 04 Jun 2024
Published online: 27 Feb 2025 *

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