Title: New dual-V_th assignment technique for design of low power CMOS adder

Authors: Kausar Fakir; Sudhakar S. Mande

Addresses: Deparment of Electronics and Telecommunication Engineering, Ramrao Adik Institute of Technology, Navi Mumbai, India ' Deparment of Electronics and Telecommunication Engineering, Don Bosco Institute of Technology, Mumbai, India

Abstract: A novel design of sensitivity-based dual threshold voltage (V_th) full adder circuit is presented in this paper. Transistors of conventional CMOS full adder circuit are assigned with dual-V_th according to the sensitivity of transistors to delay variations along all paths from every input to output terms. Plackett Burman design of experiment (PBDoE) method is applied to find out sensitivity of every transistor to delay due to variation in its threshold voltage. Transistors of conventional CMOS full adder circuit, which are not sensitive to delay are assigned with high V_th. This sensitivity-based assignment of dual-V_th will help to reduce leakage power without affecting speed of the circuit. The proposed circuit is simulated in 32 nm CMOS technology. Results shows 24% reduction in leakage power of the proposed circuit compared to conventional CMOS full adder circuit. This proposed work is extended to design dual-V_th N-bit ripple carry adder (RCA).

Keywords: low power; CMOS; full adder; ripple carry adder; dual threshold voltage; Plackett Burman design of experiment; PBDoE.

DOI: 10.1504/IJPELEC.2024.142627

International Journal of Power Electronics, 2024 Vol.20 No.4, pp.301 - 317

Received: 13 Mar 2024
Accepted: 04 Jul 2024
Published online: 12 Nov 2024 *

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