Article: Fully integrated LDO based on push-pull circuitry for enhanced power management in embedded systems Journal: International Journal of Automation and Control (IJAAC) 2024 Vol.18 No.4 pp.467 - 488 Abstract: We present a fully integrated analogue LDO voltage regulator with slew rate enhancement circuitry (SREC). The SREC is employed by implementing the push-pull current booster technique to ensure fast transient responses, which increases the rapidity of the LDO providing a high-accuracy output voltage of 1.6 V for a supply voltage of 1.8-2.5 V, without any increase in power consumption. However, the typical LDO architecture suffers from the speed-power tradeoff and a large output capacitor is inevitably required, which implies an excessively large chip area. The push-pull current booster technique not only solves the rapidity-power tradeoff and suppresses the need for an output capacitor, but also enables the LDO regulator to operate stably over all load conditions as well as achieving a quick settling time. The proposed SREC-LDO design and simulation is in a standard 180 nm TSMC CMOS process, achieving a good open loop stability; with 75° phase margin under full load current and ground current consumption of 10 <i>μ</i>A. The regulation of the line and load are 0.017 mV/V and 0.003 mV/mA respectively with a 72 fs figure of merit (FOM). Inderscience Publishers - linking academia, business and industry through research

Title: Fully integrated LDO based on push-pull circuitry for enhanced power management in embedded systems

Authors: Hatim Ameziane; Kamal Zared; Hicham Akhmal; Hassan Qjidaa

Addresses: Science and Technology for the Engineer Laboratory (LaSTI), National School of Applied Sciences Khouribga (ENSA), Sultan Moulay Slimane University, B.P. 77, 25000 Khouribga, Morocco ' Faculty of Science and Technology, Sidi Mohamed Ben Abdellah University, B.P. 2202 – Route d'Imouzzer, Fez, Morocco ' Faculty of Science, Sidi Mohamed Ben Abdellah University, B.P. 1796 – Fès-Atlas, 30003, Fez, Morocco ' Faculty of Science, Sidi Mohamed Ben Abdellah University, B.P. 1796 – Fès-Atlas, 30003, Fez, Morocco

Abstract: We present a fully integrated analogue LDO voltage regulator with slew rate enhancement circuitry (SREC). The SREC is employed by implementing the push-pull current booster technique to ensure fast transient responses, which increases the rapidity of the LDO providing a high-accuracy output voltage of 1.6 V for a supply voltage of 1.8-2.5 V, without any increase in power consumption. However, the typical LDO architecture suffers from the speed-power tradeoff and a large output capacitor is inevitably required, which implies an excessively large chip area. The push-pull current booster technique not only solves the rapidity-power tradeoff and suppresses the need for an output capacitor, but also enables the LDO regulator to operate stably over all load conditions as well as achieving a quick settling time. The proposed SREC-LDO design and simulation is in a standard 180 nm TSMC CMOS process, achieving a good open loop stability; with 75° phase margin under full load current and ground current consumption of 10 μA. The regulation of the line and load are 0.017 mV/V and 0.003 mV/mA respectively with a 72 fs figure of merit (FOM).

Keywords: low-dropout; LDO; system-on-chip; SoC; power management IC; PM-IC; slew-rate enhancement circuit; SREC; settling time.

DOI: 10.1504/IJAAC.2024.139439

International Journal of Automation and Control, 2024 Vol.18 No.4, pp.467 - 488

Received: 26 Apr 2023
Accepted: 14 Aug 2023
Published online: 02 Jul 2024 *

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Title: Fully integrated LDO based on push-pull circuitry for enhanced power management in embedded systems

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