Title: An energy efficient reconfigurable architecture for multi-lead ECG signal compression

Authors: Vinod Arunachalam; N. Kumareshan

Addresses: Government College of Engineering, Dharmapuri, India ' Sri Eshwar College of Engineering, Coimbatore, India

Abstract: The most used non-invasive diagnostic technique for a wide range of cardiac disorders is an ECG, which records the heart's electrical activity over time. Compressed ECG signals are a necessary part of most electronic health systems to store and transmit data across long distances. The field programmable gate array (FPGA), a high-speed parallel compute unit, and customisable software capabilities are available with reconfigurable architecture. Consequently, this architecture is suitable for devices like ECGs, which require precise real-time computing for multi-channel signal processing. The Xilinx Zynq 7.000 SoC development board used in this work has an FPGA-based reconfigurable signal processing unit. When compressing data, the method uses fast Fourier transformation (FFT). It is possible to achieve a 90% compression rate with this system running in real-time and with minimal to no signal distortion. This method is also the only one in the industry that can reduce high-frequency noise.

Keywords: ECG; reconfigurable architecture; health system.

DOI: 10.1504/IJMEI.2024.138293

International Journal of Medical Engineering and Informatics, 2024 Vol.16 No.3, pp.287 - 293

Received: 13 Dec 2021
Accepted: 26 Feb 2022
Published online: 01 May 2024 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article