Title: A physically unclonable function architecture with multiple responses on FPGA

Authors: M.A. Muneeb; S. Nalesh; S. Kala

Addresses: Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering College Bidar, Karnataka, India ' Department of Electronics, Cochin University of Science and Technology, Kochi-22, India ' Department of Electronics and Communication Engineering, Indian Institute of Information Technology Kottayam, Kerala-686635, India

Abstract: Physically unclonable functions (PUFs) are hardware security devices that are commonly used for authentication purposes. The unique aspect of PUFs lies in the fact that they are based on the nano-scale differences in the material used, leading to different responses each time. This randomness and uniqueness enhances the security of PUFs, making them a popular choice. There are two main types of PUFs: arbiter PUF and ring oscillator PUF. Recent advancements have revealed that incorporating additional hardware in arbiter PUFs can further improve security. However, the challenge lies in protecting the PUF when it generates a single response. To overcome this, we propose an 8-bit response PUF architecture, which eliminates this vulnerability and improves the security of PUFs. The proposed architecture has been implemented on Xilinx Spartan-7 FPGA and the results have been evaluated.

Keywords: hardware security; FPGA; physically unclonable function; PUF; multiple responses.

DOI: 10.1504/IJES.2023.134117

International Journal of Embedded Systems, 2023 Vol.16 No.1, pp.67 - 74

Received: 29 Sep 2022
Received in revised form: 26 Feb 2023
Accepted: 12 Mar 2023
Published online: 11 Oct 2023 *

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