Title: An evolvable hardware system in Xilinx Virtex II Pro FPGA

Authors: Zdenek Vasicek, Lukas Sekanina

Addresses: Faculty of Information Technology, Brno University of Technology, Bozetechova 2, Brno 612 66, Czech Republic. ' Faculty of Information Technology, Brno University of Technology, Bozetechova 2, Brno 612 66, Czech Republic

Abstract: In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.

Keywords: field programmable gate arrays; FPGA; evolutionary algorithms; EA; evolvable hardware; image operators; circuit architectures; image filter evolution; virtual reconfigurable circuits; reconfigurable logic; search algorithms.

DOI: 10.1504/IJICA.2007.013402

International Journal of Innovative Computing and Applications, 2007 Vol.1 No.1, pp.63 - 73

Published online: 25 Apr 2007 *

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