Title: High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

Authors: S.K. Binu Siva Singh; K.V. Karthikeyan

Addresses: Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar, Chennai – 100119, Tamil Nadu, India ' Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar, Chennai – 100119, Tamil Nadu, India

Abstract: Some of the advantages of the DC-DC converter digital control, such as programmability and improved control algorithms, have made it more popular in modern times. As a significant part of digital control, digital pulse width modulator (DPWM) is designed to fulfill number of requirements for high efficiency. The existing DPWM framework is implemented with high resolution along high switching frequency, but mandatory counter clock frequency is higher. To manipulate this drawback, the hybrid DPWM architecture is proposed that consolidates reversible synchronous sequential counter (RSSC) and synchronous phase-shifted circuit (SPS). The RSSC is employed to count trigger signal at each clock period. Whereas, SPS circuit is employed to select the clock by the quadrant phase-shifted clocks. The coding is activated in Verilog and the proposed RSSC design is synthesised utilising Xilinx ISE.

Keywords: DPWM; digital pulse width modulator; decoder; synchronous reversible counter; synchronous phase shifted circuit; reversible synchronous sequential counter; D-flip flop; delay line output duty cycle; linearity; time resolution.

DOI: 10.1504/IJHPSA.2023.130225

International Journal of High Performance Systems Architecture, 2023 Vol.11 No.3, pp.148 - 155

Received: 22 Jun 2022
Accepted: 05 Sep 2022
Published online: 06 Apr 2023 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article