Title: 3D layout of the Spidergon-Donut on-chip interconnection network

Authors: Fadi N. Sibai; Abu Asaduzzaman; Ali Elmoursy

Addresses: Department of Electrical & Computer Engineering, Gulf University for Science and Technology, P.O. Box 7207, Hawally 32093, Kuwait ' Department of Electrical and Computer Engineering, Wichita State University, Wichita, KS 67260, USA ' Department of Electrical and Computer Engineering, University of Sharjah, P.O. Box 27272, Sharjah, UAE

Abstract: 3D integration promises to resolve many of the heat and die size limitations of 2D integrated circuits. A critical step in the design of 3D many-cores and MPSOCs is the layout of their 3D network-on-chip (NoC). In this paper, we explore and present multiple 3D layouts of the Spidergon-Donut (SD) NoC and estimate their longest wire lengths and cost requirements. For a total of 64 cores, the 4×2×8 and 2×4×8 placements result in the best longest wire delays, with the former higher 3D integration costs, while the second requiring larger chip area and through-silicon-vias (TSV) array costs. Such study helps in guiding 3D integration direction and weighing 3D NoC layout and placement alternatives.

Keywords: 3D integration; 3D on-chip networks; Spidergon-Donut network; many-core processors; wire delay; chip area; heat dissipation.

DOI: 10.1504/IJHPSA.2023.130222

International Journal of High Performance Systems Architecture, 2023 Vol.11 No.3, pp.137 - 147

Received: 04 Jun 2022
Accepted: 05 Sep 2022
Published online: 06 Apr 2023 *

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