Title: MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

Authors: Prashant S. Titare; D.G. Khairnar

Addresses: E&TC Department, D Y Patil College of Engineering, Akurdi, Pune, 411044, India ' E&TC Department, D Y Patil College of Engineering, Akurdi, Pune, 411044, India

Abstract: The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

Keywords: multiprocessors; soft core processor architecture; embedded systems; VLSI; versions like ultra large; MPSoC; multi-processor system on chip; parallel processing; FPGA; field programmable gate array; high performance; speed enhancement; arithmetic application.

DOI: 10.1504/IJHPSA.2023.130214

International Journal of High Performance Systems Architecture, 2023 Vol.11 No.3, pp.156 - 168

Received: 19 Apr 2022
Accepted: 01 Oct 2022
Published online: 06 Apr 2023 *

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