Title: Modulation technique based on low computational SVPWM for reduced switch multilevel inverter - hardware implementation

Authors: Jose Jacob; M.V. Sarin; A. Chitra; W. Razia Sultana

Addresses: Faculty of Science and Technology, University of Bolzano, Italy ' School of Electrical Engineering, Vellore Institute of Technology, Vellore-632 014, India ' School of Electrical Engineering, Vellore Institute of Technology, Vellore-632 014, India ' School of Electrical Engineering, Vellore Institute of Technology, Vellore-632 014, India

Abstract: This work envisages promoting an experimental analysis of a reduced switch asymmetrical multilevel topology when controlled with different modulation schemes. For investigation, two modulation schemes were used, i.e.: 1) SPWM - sinusoidal pulse width modulation; 2) SVPWM - space vector pulse width modulation techniques. The algorithm developed here in this work is a general one, which can be applied to any N-level inverters without much complexity as compared with standard space vector techniques. The output of the MLI is evaluated by the total harmonic distortion (THD) for both modulation techniques. A seven-level output voltage has been generated by the mentioned topology. Complete modelling by the numerical equation is done with MATLAB/Simulink tool. To give proof of the numerical results, an experimental setup has been implemented using dSPACE 1104. The effectiveness of the general space vector algorithm over SPWM technique is shown experimentally. The experimental verification reveals that the low computational SVPWM outperforms the conventional schemes.

Keywords: power converters; DC-AC; PWM inverters; SVPWM; power MOSFET; inverters.

DOI: 10.1504/IJPELEC.2023.128866

International Journal of Power Electronics, 2023 Vol.17 No.2, pp.197 - 217

Received: 09 Jan 2021
Accepted: 10 Aug 2021
Published online: 08 Feb 2023 *

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