Article: An efficient optimisation-based design of current conveyor performances Journal: International Journal of Computer Aided Engineering and Technology (IJCAET) 2023 Vol.18 No.1/2/3 pp.167 - 180 Abstract: Optimisation algorithms are increasingly used by electronic circuit designers to optimally design and size the performance of their circuits. Multi-objective optimisation algorithms have a great interest, since in most cases the problems of sizing analogue, RF and mixed-signal ICs include at least two conflicting and contradictory objectives. In the present paper, we present two evolutionary algorithms (EA) well known in the literature for their better performance in solving more difficult multi-objective problems (MOP). The performances of these proposed algorithms are first applied to some well-known mathematical benchmark functions and then to deal with the optimal sizing of current conveyor transistors in the framework of 0.18 μm technology. The most important objectives are to maximise the cut-off frequency and minimise the parasitic resistance of X-port. Pareto fronts are generated, and optimised solutions are chosen. Performance metrics of the optimisation results obtained are carried out by the CADENCE Virtuoso software. This paper discusses and shows that AEs are a priori the most adapted class of metaheuristics to be used in the field of optimal electronic circuit sizing. Inderscience Publishers - linking academia, business and industry through research

Title: An efficient optimisation-based design of current conveyor performances

Authors: Abdelaziz Lberni; Malika Alami Marktani; Abdelaziz Ahaitouf; Ali Ahaitouf

Addresses: Intelligent Systems, Geo-resources and Renewable Energies Laboratory, Faculty of Sciences and Technology, Fez, Morocco ' Intelligent Systems, Geo-resources and Renewable Energies Laboratory, School of Applied Sciences, Fez, Morocco ' Engineering Sciences Laboratory, Polydisciplinary Faculty, Taza, Morocco ' Intelligent Systems, Geo-resources and Renewable Energies Laboratory, Faculty of Sciences and Technology, Fez, Morocco

Abstract: Optimisation algorithms are increasingly used by electronic circuit designers to optimally design and size the performance of their circuits. Multi-objective optimisation algorithms have a great interest, since in most cases the problems of sizing analogue, RF and mixed-signal ICs include at least two conflicting and contradictory objectives. In the present paper, we present two evolutionary algorithms (EA) well known in the literature for their better performance in solving more difficult multi-objective problems (MOP). The performances of these proposed algorithms are first applied to some well-known mathematical benchmark functions and then to deal with the optimal sizing of current conveyor transistors in the framework of 0.18 μm technology. The most important objectives are to maximise the cut-off frequency and minimise the parasitic resistance of X-port. Pareto fronts are generated, and optimised solutions are chosen. Performance metrics of the optimisation results obtained are carried out by the CADENCE Virtuoso software. This paper discusses and shows that AEs are a priori the most adapted class of metaheuristics to be used in the field of optimal electronic circuit sizing.

Keywords: metaheuristics; optimisation algorithms; evolutionary algorithms; analogue IC design; current conveyor; multi-objective optimisation; Pareto front; CMOS technology.

DOI: 10.1504/IJCAET.2023.127794

International Journal of Computer Aided Engineering and Technology, 2023 Vol.18 No.1/2/3, pp.167 - 180

Received: 20 Mar 2020
Accepted: 26 Jun 2020
Published online: 19 Dec 2022 *

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Title: An efficient optimisation-based design of current conveyor performances

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