Title: Design and simulation of logic gates using single electron transistors at room temperature

Authors: Aranggan Venkataratnam, Ashok K. Goel

Addresses: Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, MI, USA. ' Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, MI, USA

Abstract: The Single Electron Transistor (SET) is a nanoscale three terminal device that provides current conduction characteristics comparable to a MOSFET and can be used for developing nanoscale logic circuits. In this paper, we have determined the design parameters of an SET to observe current oscillations at room temperature. These parameters have been used to design SET-based logic gates for room temperature operation. The circuit architectures of the proposed SET-based logic gates are identical to the corresponding CMOS gates. Complementary operations of an SET as n- and p-type devices were achieved by controlling the charge on the SET island by using the appropriate tuning gate voltages. We have proposed room temperature designs for the NOT, NOR, NAND, And-Or-Invert (AOI) and Or-And-Invert (OAI) gates. Their operations have been verified by simulations with a SPICE package which includes the SET-SPICE model.

Keywords: nanotechnology; nanoscale technology; single electron transistors; SET; CMOS; logic gates; logic gate design; simulation; room temperature; nanoscale logic circuits.

DOI: 10.1504/IJCSE.2006.012770

International Journal of Computational Science and Engineering, 2006 Vol.2 No.3/4, pp.179 - 188

Available online: 14 Mar 2007 *

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