Authors: Philip M. Walker, Hiroshi Mizuta
Addresses: Microelectronics Research Centre, University of Cambridge, Cambridge CB3 0HE, UK. ' Department of Physical Electronics, Tokyo Institute of Electronics, Tokyo 152-8552, Japan; School of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, UK
Abstract: In this paper, we have investigated the effect of a single Grain Boundary (GB) on the performance of decananometre-scale Thin Film Transistors (TFTs) by using the calibrated energy balance transport model and a continuous trap state distribution at the GB. We have found that the GB potential barrier suppresses the subthreshold slope and leakage current in devices, where the DIBL effect and punchthrough currents significantly degrade device performance. We have also found that the drift-diffusion model underestimates the drain current in the single-GB TFT and the velocity overshoot effect becomes significant in the short channel regime. Inclusion of trap-to-band and band-to-band tunnelling models into our simulations have shown that the subthreshold leakage current has a significant field dependence in the negative gate bias regime.
Keywords: poly-silicon; grain boundary; energy balance modelling; thin-film transistors; TFTs; nanoscale technology; nanotechnology; transport models; continuous trap state distribution; drain current; subthreshold slope; leakage current; DIBL effect; punchthrough currents; tunnelling models; simulation.
International Journal of Computational Science and Engineering, 2006 Vol.2 No.3/4, pp.148 - 157
Available online: 14 Mar 2007 *Full-text access for editors Access for subscribers Purchase this article Comment on this article