Title: Performance assessment of adaptive core mapping for NoC-based architectures

Authors: Aruru Sai Kumar; T.V.K. Hanumantha Rao

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Warangal, India ' Department of Electronics and Communication Engineering, National Institute of Technology Warangal, India

Abstract: In this trending technology of network-on-chip, the large number of cores embedded on-chip had a rapid growth resulting in performance degradation. Many methodologies came into existence to improve the performance of a network. In this research paper, an adaptive core mapping technique is implemented to minimise the latency and improve the system performance. The traditional method calculation of NAD, PVR and WMD parameters is evaluated in this core mapping strategy. The core mapping region is obtained from the calculation of NAD and PVR, whereas the communication energy between the cores is obtained through WMD. The sequence for mapping the cores is implemented through the lowest communication energy, i.e., in ascending order and this mapping technique is applied to the PARSEC benchmark suite for the evaluation. The proposed adaptive core mapping technique is evaluated using the GEM5 simulator. The simulated outcome of this technique has outperformed both the latency and system performance compared with FASA, FARM and NMAP techniques. The simulations and synthesis carried out through the Vivado Design Suite 2018.3 outperformed the metrics such as total latency, power consumption and the core mapping time compared to other algorithms.

Keywords: system-on-chip; SoC; network-on-chip; NoC; core; core mapping; node average distance; NAD; placing unmapped vertices region; PVR; communication energy; benchmarks; latency; system performance.

DOI: 10.1504/IJES.2022.127149

International Journal of Embedded Systems, 2022 Vol.15 No.5, pp.395 - 403

Received: 17 Feb 2021
Accepted: 03 Aug 2021
Published online: 23 Nov 2022 *

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