Authors: Pulkit Singh; K. Abhimanyu Kumar Patro; Bibhudendra Acharya; Rahul Kumar Chaurasiya
Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Raipur – 492010, Chhattisgarh, India ' Department of Mechatronics, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal – 576104, Karnataka, India ' Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Raipur – 492010, Chhattisgarh, India ' Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology Bhopal, Bhopal – 462003, Madhya Pradesh, India
Abstract: With the advancement of communication networks, information security has become extremely crucial in storage and transmission. As images are used in most of the networks, hence image security is becoming a challenging task. This paper proposes two hardware architectures of Lilliput lightweight block cipher. These hardware architectures are implemented on FPGA and ASIC platforms compared with state-of-the-art designs. In these architectures, first, 8-bit and then 16-bit serial structures are designed to implement. The serialised designs of 8-bit and 16-bit imply low area by consuming less number of slices. Finally, these serialised architectures are utilised for image encryption with the help of a controller. The simulation results and security analysis for hardware generated encrypted images show the better performance of proposed architectures and stronger resistance against entropy attack, differential attack, and statistical attacks.
Keywords: security; lightweight cryptography; FPGA; ASIC; image encryption; Lilliput cipher; IoT; hardware implementation; low resource devices; throughput.
International Journal of Ad Hoc and Ubiquitous Computing, 2022 Vol.41 No.4, pp.205 - 220
Received: 11 Jan 2021
Accepted: 26 Dec 2021
Published online: 07 Nov 2022 *