Title: A 600 mV +20 dBm IIP₃ CMOS LNA with g_m smoothening auxiliary path for 2.4 GHz wireless applications

Authors: D. Sharath Babu Rao; V. Sumalatha

Addresses: Electronics and Communication Engineering Department, JNTUA, Anantapuramu-515002, Andhra Pradesh, India ' Electronics and Communication Engineering Department, JNTUA, Anantapuramu-515002, Andhra Pradesh, India

Abstract: CMOS low noise amplifiers (LNA's) finds a large-scale of applications in biomedical applications and other mission sensors which include cordless telephones, wireless keyboards, and radio equipment. For radio-frequency (RF) applications where signal frequencies are high, consequences of intermodulation distortion results from the nonlinearities of the MOS transistors used in the LNA. As it is impracticable to eradicate nonlinearities completely, second-order nonlinearities were added in out of phase with the third-order nonlinearities in derivative and modified derivative methods which suppress the third-order nonlinearities up to an input intercept point (IIP3) of 8 dBm only. In this article, proposed LNA reduces the nonlinearity interaction increases the IIP3 performance up to 12 dBm using the common source differential architecture with PMOS loads in the auxiliary path. The proposed LNA offers gain (S21) of 12 dB operates at ultra-low voltage supply headroom of 600 mV with good stability deemed as a favourable requirement for low power wireless applications.

Keywords: 802.11 b/g/n; wireless LAN; wireless sensor networks; WSN; wireless personal area networks; WPAN; low noise amplifier; LNA; BSIMv3; cascode LNA; folded cascode LNA; MDS technique.

DOI: 10.1504/IJICA.2022.124236

International Journal of Innovative Computing and Applications, 2022 Vol.13 No.3, pp.127 - 137

Received: 19 Mar 2020
Accepted: 06 May 2020
Published online: 19 Jul 2022 *

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