Authors: Suman Bhowmik
Addresses: Intel, Bangalore, India
Abstract: Leakage power dissipation contributes to a considerable amount of total power dissipation for the circuit designed below 50 nm technology. In this paper two techniques are proposed to reduce leakage power as well as total power of logic circuits by circuit level modification. The techniques use extra foot transistors along with capacitor to reduce leakage power. As a basic building block, NAND and NOR gate are modified accordingly for leakage reduction. The proposed techniques have also been extended to a larger circuit to confirm its power utility. Leakage power dissipation, total power dissipation, energy and the trade-off among them of the new designs have been discussed and compared with the results of conventional CMOS circuits. The best adder configuration exhibits more than 20% saving in leakage and 28% saving in total power. For circuit design and simulation, virtuoso Cadence tool at 45 nm technology has been used.
Keywords: leakage power; CMOS; delay.
International Journal of Computer Aided Engineering and Technology, 2022 Vol.16 No.4, pp.478 - 487
Received: 03 Jun 2019
Accepted: 11 Nov 2019
Published online: 06 Jul 2022 *