Title: Design and implementation of an ASIP for SHA-3 hash algorithm

Authors: Yavar Safaei Mehrabani; Roghayeh Ataie; Mohammad Hossein Shafiabadi; Abolghasem Ghasempour

Addresses: Department of Computer Engineering, North Tehran Branch, Islamic Azad University, Tehran, Iran ' Department of Electrical Engineering, University of Jiroft, Jiroft, Iran ' Department of Computer Engineering, Islam Shahr Branch, Islamic Azad University, Tehran, Iran ' Department of Computer Engineering, Islam Shahr Branch, Islamic Azad University, Tehran, Iran

Abstract: In recent years, application specific instruction set processor (ASIP) has attracted many researchers attention. These processors resemble application specific integrated circuits (ASICs) and digital signal processors (DSPs) from the performance and flexibility point of view, respectively. In other words, ASIP makes compromise between performance and flexibility criteria. The SHA-3 hashing algorithm has been introduced as the safest and the newest algorithm in 2015 as a global standard. In this paper, a processor with specific instruction set is designed and implemented with regard to variant execution steps of this algorithm. In order to do the modelling and simulation of the processor, we have used the VHDL hardware description language and the ModelSim SE 6.1 tool. Moreover, in order to implement it on a field programmable gate array (FPGA) platform we have used the Xilinx ISE 10.1 tool. The implemented processor has 213.356 MHz operating frequency and 3.004 Mbps throughput.

Keywords: application specific instruction set processor; ASIP; processor; instruction set architecture; ISA; hash; SHA-3 algorithm.

DOI: 10.1504/IJICS.2022.122375

International Journal of Information and Computer Security, 2022 Vol.17 No.3/4, pp.285 - 309

Received: 06 Nov 2018
Accepted: 01 Apr 2019
Published online: 22 Apr 2022 *

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