Article: Asynchronous dynamic arbiter for network on chip Journal: International Journal of Computer Applications in Technology (IJCAT) 2021 Vol.67 No.4 pp.370 - 382 Abstract: In modern Network on Chip (NoC), communicating blocks are synchronised with different clock rates. However, system performances may present a bottleneck that can be remedied only by considering the notion of communication asynchrony. The implementation of a high-performance asynchronous NoC router requires the design of dynamic arbitration structures to lower packets latency, and thus, increase throughput. Also, the dissipated power needs to be as small as possible. This paper presents a design approach of asynchronous dynamic arbiters to be implemented in NoC routers. The design steps begin by State Transition Graph (STG) as specification model and generate a Quasi-Delay-Insensitive (QDI) arbiter implemented by C-element gates. The designed arbiter communicates with the shared resources by using a 4-phases (Req/Ack) handshaking protocol. Arbiter performances have been evaluated through the implementation of an asynchronous 2D-Mesh NoC router in FPGA (Virtex 5) and ASIC (28 nm) technologies. Experimental results show that the proposed router exhibits higher performances compared to its counterparts. In ASIC design, this router achieves low power (3.8 mW), low area (0.009 mm²), low latency (1.53 ns) and high packet throughput (1562 Mflit/s). Inderscience Publishers - linking academia, business and industry through research

Title: Asynchronous dynamic arbiter for network on chip

Authors: Abdelkrim Zitouni; Bouraoui Chemli

Addresses: Department of Physics, College of Science & Humanities Jubail, Imam Abdulrahman Bin Faisal University, Dammam, Jubail 31961, Saudi Arabia ' Department of Physics, Electronics and Microelectronics Laboratory, Faculty of Sciences of Monastir, University of Monastir, Monastir, Tunisia

Abstract: In modern Network on Chip (NoC), communicating blocks are synchronised with different clock rates. However, system performances may present a bottleneck that can be remedied only by considering the notion of communication asynchrony. The implementation of a high-performance asynchronous NoC router requires the design of dynamic arbitration structures to lower packets latency, and thus, increase throughput. Also, the dissipated power needs to be as small as possible. This paper presents a design approach of asynchronous dynamic arbiters to be implemented in NoC routers. The design steps begin by State Transition Graph (STG) as specification model and generate a Quasi-Delay-Insensitive (QDI) arbiter implemented by C-element gates. The designed arbiter communicates with the shared resources by using a 4-phases (Req/Ack) handshaking protocol. Arbiter performances have been evaluated through the implementation of an asynchronous 2D-Mesh NoC router in FPGA (Virtex 5) and ASIC (28 nm) technologies. Experimental results show that the proposed router exhibits higher performances compared to its counterparts. In ASIC design, this router achieves low power (3.8 mW), low area (0.009 mm²), low latency (1.53 ns) and high packet throughput (1562 Mflit/s).

Keywords: asynchronous dynamic arbiter; STG; C-element; NoC router; FPGA/ASIC designs.

DOI: 10.1504/IJCAT.2021.122349

International Journal of Computer Applications in Technology, 2021 Vol.67 No.4, pp.370 - 382

Received: 18 Sep 2020
Accepted: 26 Feb 2021
Published online: 21 Apr 2022 *

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Title: Asynchronous dynamic arbiter for network on chip

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