Title: Design, optimisation and implementation of a DCT/IDCT-based image processing system on FPGA
Authors: Shensheng Tang; Monali Sinare; Yi Zheng
Addresses: St. Cloud State University, St. Cloud, Minnesota 56301, USA ' St. Cloud State University, St. Cloud, Minnesota 56301, USA ' St. Cloud State University, St. Cloud, Minnesota 56301, USA
Abstract: In this paper, a Discrete Cosine Transform (DCT) and its inverse transform IDCT are designed and optimised for FPGA using the Xilinx VIVADO High-Level Synthesis (HLS) tool. The DCT and IDCT algorithms along with a filter logic written by C/C++ are simulated for functional verification and optimised through HLS and packaged as custom IPs. The IPs are incorporated into a VIVADO project to form an image processing system for hardware validation. The VIVADO design along with a Xilinx SDK application written by C language is implemented on a Zynq FPGA development board, ZedBoard. A C# GUI is developed to transfer image data to/from the FPGA and display the original and processed images. Experimental results are presented with discussion. The FPGA development method including the DCT/IDCT IP design, optimisation and implementation via HLS as well as the VIVADO project integration can be extended to a wider range of FPGA applications.
Keywords: DCT; IDCT; FPGA; VIVADO HLS; IP; ZedBoard; GUI; C/C++; Verilog; C#; optimisation; C/RTL co-simulation; hardware validation.
International Journal of Computer Applications in Technology, 2021 Vol.67 No.4, pp.303 - 323
Received: 07 Jan 2021
Accepted: 15 Feb 2021
Published online: 21 Apr 2022 *