Authors: Mohammad Samadi Gharajeh
Addresses: Young Researchers and Elite Club, Tabriz Branch, Islamic Azad University, Tabriz, Iran
Abstract: Multiplying the BCD numbers by powers of 10 is one of the essential operations in complex circuits. This paper proposes a novel multiplier to multiply BCD numbers by powers of 10. It uses a value-based architecture instead of the static architecture that is used in general multipliers. The proposed multiplier is composed of multiple embedded sub-multipliers so that each one multiplies one of the BCD numbers by the powers of 10. The multiplication results of each sub-multiplier are calculated by some mathematical equations based on input binary bits. Furthermore, the final output of the proposed multiplier are produced based the multiplication results of the sub-multipliers with the aid of a proposed selection unit. Comparison results demonstrate that the proposed multiplier surpasses some of the existing general multipliers in term of the number of logic gates. The proposed architecture is programmed by the VHDL codes and is simulated using the active-HDL simulation environment.
Keywords: electronic circuit; multiplication; multiplier; BCD number; power of 10; value-based architecture; computer architecture; computer system; arithmetic; circuit complexity; VHDL; active-HDL; simulation.
International Journal of Computer Aided Engineering and Technology, 2022 Vol.16 No.3, pp.306 - 327
Received: 13 Nov 2018
Accepted: 10 Jul 2019
Published online: 11 Apr 2022 *