Title: Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures

Authors: Chawki Benchehida; Mohammed Kamel Benhaoua; Houssam Eddine Zahaf; Giuseppe Lipari

Addresses: Univ. Oran1 – LAPECI Laboratory, Oran, Algeria; Univ. Lille, CNRS, Centrale Lille, UMR 9189 CRIStAL, F-59000 Lille, France ' Univ. Oran1 – LAPECI Laboratory, Oran, Algeria; Univ. Mustapha Stambouli, Mascara, Algeria ' Univ. Nantes – LS2N UMR 6004, Nantes, France ' Univ. Lille, CNRS, Centrale Lille, UMR 9189 CRIStAL, F-59000 Lille, France

Abstract: The network-on-chip (NoC) provides a viable solution to bus-contention problems, that occur in classical manycore architectures. However, NoC complex design requires a particular attention to support the execution of real-time workloads. In this paper, we consider task-to-core allocation and inter-task communications, to guarantee the respect of timing constraints. In addition, we address task-to-main-memory communications, as it generates additional traffic. Rather than separating the problems of task-to-core allocation, inter-task communications, and memory-to-task data transfers separately, we tackle these problems at the same time for a set of real-time tasks modeled using directed acyclic graphs (DAGs). We propose an allocation algorithm and sequence of transformations to simplify the problem resolving and handle its combinatorial explosion. We evalaute the effectiveness of the proposed approaches using a large set of synthetic experiments.

Keywords: real-time systems; NoC; network-on-chip; SDRAM; partitioned scheduling; task allocation.

DOI: 10.1504/IJHPSA.2022.121877

International Journal of High Performance Systems Architecture, 2022 Vol.11 No.1, pp.1 - 11

Received: 03 Feb 2021
Accepted: 14 May 2021
Published online: 07 Apr 2022 *

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