Title: VLSI system architecture optimisation for DLMS adaptive filter using PPG based multiplier

Authors: Y. Premson; R. Sakthivel

Addresses: School of Electronics Engineering, Vellore Institute of Technology University, Vellore – 632014, Tamil Nadu, India ' School of Electronics Engineering, Vellore Institute of Technology University, Vellore – 632014, Tamil Nadu, India

Abstract: A partial product generator based multiplier is used to reduce the complexity of multiplication operation. This multiplier, designed using decoders and and-or cells in earlier work are modified with a multiplexer to improve the speed and area of the architecture. When approximate multipliers are employed, the complexity can be further reduced and they can be used for highly data intensive processing applications like image restoration, pattern classification etc., where an approximate operation is enough in most of the cases. A delayed least mean squared (LMS) adaptive filter is designed using Xilinx ISE and implemented in Spartan-6 development board, which itself contains an FIR filter, and modified using multiplexer and approximate compressor type adder (ACA) combination. For the FIR filter part alone, the percentage decrease in maximum path delay is 40 % and that in total area is 37%. For the delayed least mean squared (DLMS) adaptive filter these values are 17 and 47 respectively.

Keywords: adaptive DLMS filter; AND-OR cell; approximate compressor adder; error computation; partial product generator; VLSI system architecture; weight-updation.

DOI: 10.1504/IJSSE.2021.121463

International Journal of System of Systems Engineering, 2021 Vol.11 No.3/4, pp.352 - 362

Received: 05 Aug 2020
Accepted: 09 Nov 2020
Published online: 14 Mar 2022 *

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