Title: Methods of designing electrical equipment for testing very large scale integrated circuit

Authors: K.K. Smirnov; A.V. Nazarov; V.V. Blinov

Addresses: Scientific Research Institute of System Analysis (SRISA/NIISI RAS), Nakhimovsky Ave., 36, Building 1, 117218, Moscow, Russia; Moscow Aviation Institute (National Research University), Volokolamskoe sh, 4, 125993, Moscow, Russia ' Moscow Aviation Institute (National Research University), Volokolamskoe sh, 4, 125993, Moscow, Russia ' Scientific Research Institute of System Analysis (SRISA/NIISI RAS), Nakhimovsky Ave., 36, Building 1, 117218, Moscow, Russia

Abstract: Due to the constant increase in the level of integration of modern integrated circuits, more stringent requirements are imposed not only on the effectiveness of the methods of their functional control, but also on the timing of the development of electrical equipment. Equipment in the new conditions should work at lower supply voltages, at increased operating frequencies, with a number of chip pins is measured in thousands. The dimension and complexity of the task of designing electrical equipment also increase sharply, and the need to maintain the quality of very large scale integrated (VLSI) circuit development at the proper level leads to a sharp increase in the timing of their commissioning. The way out of this situation lies in the development of new VLSI testing methods and new methods for electrical equipment designing. The paper proposes one of such fundamental approaches, paving the way for full automation of the technological process of designing test solutions, ensuring effective production functional control of VLSI in an acceptable time frame. The method is based on establishing the exact correspondence of mathematical and topological models of VLSI chip. The problems of electrical equipment designing include: the need to take into account the peculiarities of wiring of differential pairs on printed board of electrical equipment, configuring diverse equipment, the avalanche-like growth in the volume and complexity of tests, the increase in the operating frequencies of modern VLSI, numerous technological and other limitations. To solve them, the paper proposes a number of constructive methods, including exact methods of local optimisation.

Keywords: automatic design; ultra-large integrated circuits; microchips testing; software; testing of integrated circuits; software; mathematical models.

DOI: 10.1504/IJNT.2021.118161

International Journal of Nanotechnology, 2021 Vol.18 No.9/10, pp.847 - 868

Published online: 13 Oct 2021 *

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