Article: FPGA based implementation of reversible data hiding scheme for content verification and quality access control of image Journal: International Journal of Signal and Imaging Systems Engineering (IJSISE) 2021 Vol.12 No.3 pp.93 - 107 Abstract: Reversible watermarking (RW) is the type of lossless data-hiding technique where the original object can be retrieved pixel by pixel at the receiver. This paper represents the hardware design for the spread spectrum (SS) based content-dependent RW in the Discrete Cosine Transform (DCT) domain for quality access control of digital image. The watermark is generated from DCT coefficients of a set of blocks (8 × 8) selected by a secret key. It is inserted into another set of DCT blocks (8×8) using SS modulation. In the decoder, the original watermark is generated and extracted by the secret key. The RW system is investigated in very-large-scale-integration with field-programmable-gate-array for real-time implementation of (N × N) image block. The framework is judged and verified about device utilisation parameters, power consumption, and bit rate. The encoder and decoder achieve the highest average throughput of 79.7025 Megabyte/s. This design also saves 88.46% more power than the related works. Inderscience Publishers - linking academia, business and industry through research

Title: FPGA based implementation of reversible data hiding scheme for content verification and quality access control of image

Authors: Poulami Jana; Amit Phadikar; Himadri Mandal

Addresses: Department of Electronics and Telecommunication Engineering, Bengal Institute of Polytechnic, Birbhum, 731124, West Bengal, India ' Department of Information Technology, MCKV Institute of Engineering, Liluah, Howrah, 711204, West Bengal, India ' Department of Electronics and Communication Engineering, Calcutta Institute of Technology, Uluberia, Howrah, 711316, West Bengal, India

Abstract: Reversible watermarking (RW) is the type of lossless data-hiding technique where the original object can be retrieved pixel by pixel at the receiver. This paper represents the hardware design for the spread spectrum (SS) based content-dependent RW in the Discrete Cosine Transform (DCT) domain for quality access control of digital image. The watermark is generated from DCT coefficients of a set of blocks (8 × 8) selected by a secret key. It is inserted into another set of DCT blocks (8×8) using SS modulation. In the decoder, the original watermark is generated and extracted by the secret key. The RW system is investigated in very-large-scale-integration with field-programmable-gate-array for real-time implementation of (N × N) image block. The framework is judged and verified about device utilisation parameters, power consumption, and bit rate. The encoder and decoder achieve the highest average throughput of 79.7025 Megabyte/s. This design also saves 88.46% more power than the related works.

Keywords: content dependent watermarking; access control; DCT; discrete cosine transform; VHDL; very-high-speed-integrated-circuit-hardware-description-language; FPGA; field-programmable-gate-array.

DOI: 10.1504/IJSISE.2021.117916

International Journal of Signal and Imaging Systems Engineering, 2021 Vol.12 No.3, pp.93 - 107

Accepted: 18 May 2021
Published online: 04 Oct 2021 *

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Title: FPGA based implementation of reversible data hiding scheme for content verification and quality access control of image

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