Title: Performance assessment of double gate graded junction-less-FET device with temperature variations

Authors: Sanjeet Kumar Sinha

Addresses: School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

Abstract: This paper reports a simulation-based study of double gate graded channel junctionless metal field effect transistor (MOSFET) incorporating the effects of doping engineering. The proposed device has been optimised to study the effect of temperature on the device characteristics such as surface potential, transfer characteristics, I_ON/I_OFF ratio and, threshold voltage. To justify the enhanced performance of the graded double gate junctionless (DG-JL) FET, it is compared with non-graded DG-JL-FET. To design and optimise the device, the simulation as a tool takes part in understanding of basic physics. The graded DG-JL-FET has better performance over the conventional DG-JL-FET, in terms of I_ON/I_OFF ratio. The temperature effects on various parameters for 1:3 graded structure are obtained and compared with conventional non-graded structure. The shift in potential towards one side and deeper in case of graded structures, I_OFF current reduced significantly without affecting I_ON current. The threshold voltage roll-off with temperature is found slower in graded structure than that in conventional non-graded structure. In this work, visual TCAD simulation tool is used to simulate the electrical characteristics of the proposed device.

Keywords: MOSFET; TFET; temperature; junctionless.

DOI: 10.1504/IJNP.2021.114900

International Journal of Nanoparticles, 2021 Vol.13 No.1, pp.33 - 41

Received: 13 Jul 2020
Accepted: 28 Aug 2020
Published online: 11 May 2021 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article