Title: Hardware implementation of a modified SSD LDPC decoder

Authors: A. Rajagopal; K. Karibasappa; K.S. Vasundara Patel

Addresses: Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bengaluru, India ' Department of Electronics and Communication Engineering, Dayananda Sagar Academy of Technology and Management, Bengaluru, India ' Department of Electronics and Communication Engineering, BMS College of Engineering, Bengaluru, India

Abstract: In this work, a modification approach to the simplified soft distance (SSD) algorithm is discussed by considering soft Euclidean squared distance as a performance metric. The SSD algorithm is theoretically independent of the signal to noise ratio of the received signal. Multiplication and addition terms are the only constituents of this algorithm which reduces the complexity. In this paper, an attempt has been made to compare and analyse the performance of modified SSD with other popular algorithms such as SPA, SSPA, and LogSPA. The algorithm is implemented on Virtex-5 xc5vlx110t FPGA kit to observe the real time implications and draw apt conclusions. From the FPGA results, this paper aims to conclude the performance of modified SSD is similar to that of LogSPA with changes observed as improved throughput speed and improved bit error rate (BER).

Keywords: simplified soft distance; SSD; low density parity check; LDPC; field programmable gate array; FPGA; bit error rate; BER; sum product algorithm; SPA; simplified sum product algorithm; SSPA; logarithmic sum product algorithm; LogSPA.

DOI: 10.1504/IJCAET.2021.114497

International Journal of Computer Aided Engineering and Technology, 2021 Vol.14 No.3, pp.426 - 440

Received: 13 Jul 2018
Accepted: 23 Oct 2018
Published online: 26 Apr 2021 *

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