Article: Low power pulsed flip-flop with clock gating and conditional pulse enhancement Journal: International Journal of Automation and Control (IJAAC) 2021 Vol.15 No.2 pp.259 - 274 Abstract: A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively. Inderscience Publishers - linking academia, business and industry through research

Title: Low power pulsed flip-flop with clock gating and conditional pulse enhancement

Authors: Kuruvilla John; R.S. Vinod Kumar; S.S. Kumar

Addresses: Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thucklay, Tamil Nadu, 629180, India; Faculty of Electronics and Communication Engineering, Providence College of Engineering, Chengannur, Kerala, 689122, India ' Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thucklay, Tamil Nadu, 629180, India ' Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thucklay, Tamil Nadu, 629180, India

Abstract: A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Keywords: pulse flip-flop; P-FF; low power; implicit; explicit; clock gating.

DOI: 10.1504/IJAAC.2021.113342

International Journal of Automation and Control, 2021 Vol.15 No.2, pp.259 - 274

Received: 08 Apr 2019
Accepted: 15 Oct 2019
Published online: 01 Mar 2021 *

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Title: Low power pulsed flip-flop with clock gating and conditional pulse enhancement

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