Title: Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Authors: Jean Shilpa V; P.K. Jawahar

Addresses: Department of Electronics and Communication, B.S. Abdur Rahman Crescent Institute of Science and Technology, Chennai, 600048, India ' Department of Electronics and Instrumentation, B.S. Abdur Rahman Crescent Institute of Science and Technology, Chennai, 600048, India

Abstract: Heterogeneous multi-core processors aim at overall performance improvement of computations for applications in the field of computing. It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor. Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics. The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software. Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52% performance improvement by top level pipelining.

Keywords: hybrid CPU-FPGA architecture; HCF; field programmable gate array; FPGA; fixed core; custom core.

DOI: 10.1504/IJSCC.2021.113239

International Journal of Systems, Control and Communications, 2021 Vol.12 No.1, pp.28 - 45

Accepted: 09 Feb 2020
Published online: 25 Feb 2021 *

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