Title: ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architectures

Authors: Anil Kumar; Basavaraj Talawar

Addresses: Systems, Parallelization and Architecture Research Lab (SPARK-Lab), Department of Computer Science and Engineering, National Institute of Technology Karnataka Surathkal, Mangalore 575-025, Karnataka, India ' Systems, Parallelization and Architecture Research Lab (SPARK-Lab), Department of Computer Science and Engineering, National Institute of Technology Karnataka Surathkal, Mangalore 575-025, Karnataka, India

Abstract: Network-on-chips (NoCs) have emerged as a scalable alternative to traditional bus and point-to-point architectures, it has become highly sensitive as the number of cores increases. Simulation is one of the main tools used in NoC for analysing and testing new architectures. To achieve the best performance vs. cost trade-off, simulators have become an essential tool. Software simulators are too slow for evaluating large scale NoCs. This paper presents a framework which can be used to analyse overall performance of 2D and 3D NoC architectures which is fast and accurate. This framework is named as ensemble learning-based accelerator (ELBA-NoC) which is built using random forest regression algorithm to predict parameters of NoCs. On 2D, 3D NoC architectures, ELBA-NoC was tested and the results obtained were compared with extensively used Booksim NoC simulator. The framework showed an error rate of less than 5% and an overall speedup of up to 16 K×.

Keywords: network-on-chip; NoC; 2D NoC; 3D NoC; simulation; performance modelling; machine learning; prediction; regression; ensemble learning; random forest; Booksim; performance; power; area; router; traffic pattern.

DOI: 10.1504/IJCSE.2020.113176

International Journal of Computational Science and Engineering, 2020 Vol.23 No.4, pp.319 - 335

Received: 21 Jan 2020
Accepted: 02 Jul 2020

Published online: 10 Feb 2021 *

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