Title: Hybrid PWM modulated cross switched asymmetrical multilevel inverter with reduced number of conducting devices
Authors: Thamizharasan Sandirasegarane; J. Maalmarugan; C. Krishnakumar
Addresses: Department of Electrical and Electronics Engineering, Saranathan College of Engineering, Tiruchirapalli, Tamilnadu-620012, India ' Department of Electrical and Electronics Engineering, Sri Ranganathar Institute of Engineering and Technology, Coimbatore, Tamilnadu-641110, India ' Department of Electrical and Electronics Engineering, Saranathan College of Engineering, Tiruchirapalli, Tamilnadu-620012, India
Abstract: This paper brings out a new topology for a cascaded multilevel inverter (CMLI) with a view to reduce the number of power switching devices in the path of the current. The philosophy suggests the integration of a low voltage pulse width modulated (PWM) inverter along with a high voltage fundamental switching inverter to produce the specified number of output levels by switching the series connected DC sources of high voltage inverter in an additive and or subtractive combination with low voltage PWM inverter. It invites a hybrid PWM approach to the process of generating the pulses for synthesising the stepped nature in conjunction with the variable pulse width output. The use of a smaller number of switches to reach the output voltage show cases the ability of the modular architecture to expand the scope of CMLI. The artefacts of a field programmable gate array (FPGA) foster to realise its implementation in pulse generation for switching the devices and verify the simulated results for steady state and dynamic load conditions in order to attach a viability perspective for its use in the real world.
Keywords: field programmable gate array; pulse width modulation inverters; hybrid PWM; reduced gate drivers.
International Journal of Power Electronics, 2021 Vol.13 No.2, pp.166 - 182
Received: 16 Jan 2018
Accepted: 24 Jul 2018
Published online: 15 Dec 2020 *