Title: Multi-parametric optimisation of the modular computer architecture

Authors: Lev Kirischian, Vadim Geurkov, Valeri Kirischian, Irina Terterian

Addresses: Department of Electrical and Computer Engineering, Embedded Reconfigurable Systems Laboratory (ERSL), Ryerson University, 350 Victoria Street, Toronto, Ontario, M5B 2K3, Canada. ' Department of Electrical and Computer Engineering, Embedded Reconfigurable Systems Laboratory (ERSL), Ryerson University, 350 Victoria Street, Toronto, Ontario, M5B 2K3, Canada. ' Department of Electrical and Computer Engineering, Embedded Reconfigurable Systems Laboratory (ERSL), Ryerson University, 350 Victoria Street, Toronto, Ontario, M5B 2K3, Canada. ' Department of Electrical and Computer Engineering, Embedded Reconfigurable Systems Laboratory (ERSL), Ryerson University, 350 Victoria Street, Toronto, Ontario, M5B 2K3, Canada

Abstract: The paper describes an approach that allows optimisation of computing architecture selection in case of multi-parametric requirements. The proposed method is oriented to systems combined from modular components. The approach is based on decomposition of a multi-dimensional design space into multiple two-dimensional subdesign spaces. The paper presents the procedure that drastically reduces the number of architectural variants to be analysed. This has become possible by the presentation of each subdesign space in a form of a tree, hierarchical arrangement, and further pruning of subdesign spaces. The proposed approach is applicable to any system architecture based on modules with known performance parameters. As a result, the proposed method has allowed selection of the architecture, which satisfies multiple performance constrains (e.g., performance, cost, power consumption, reliability, etc.), in a small time range. The implementation of the method for the architectural optimisation of the reconfigurable data-stream processors, which are based on the Field Programmable Gate Array (FPGA) devices, is also discussed.

Keywords: high-level architectural synthesis; architecture optimisation; design space; reconfigurable computing; field programmable gate array; FPGA; data-stream processing; tree arrangements; modular computer architecture; modular design.

DOI: 10.1504/IJTPM.2006.011256

International Journal of Technology, Policy and Management, 2006 Vol.6 No.3, pp.327 - 346

Published online: 09 Nov 2006 *

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