Title: A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
Authors: A. Shailaja; Krishnamurthy Gorappa Ningappa
Addresses: Visvesvaraya Technological University, VTU Main Rd, Jnana Sangama, Machhe, Belgaum, Karnataka 590018, India ' BNM Institute of Technology, 12th Main Road, 27th Cross, Banashankari Stage II, Banashankari, Bengaluru, Karnataka 560070, India
Abstract: The rapid growing impact of light weight applications (RFID tags, smartcards, sensor nodes and FGPAs) makes security a major concern in communication systems. Light weight cryptographic algorithm or ciphers can provide security and confidentiality of data or messages transmitted. In this paper, we proposed low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system (XTEA-LCS method) to improve the efficiency of encryption and decryption process. The key is the major concern of the encryption and decryption process. So in this research random numbers generated using LCS was used for key purpose, which efficiently reduced area and execution time of XTEA-LCS method and improved the system security. The XTEA-LCS method has been implemented in the Xilinx tool using Verilog code on different Virtex devices such as Virtex6, Low Power Virtex-6 (LP Virtex-6), and Virtex-7. In the field programmable gate array (FPGA) implementation, the number of look up tables (LUTs), slices and flip flops reduced and the frequency increased compared to the existing methods: QTL algorithm, DROM-CSLA-QTL and XTEA. The XTEA-LCS methodology improves the FPGA performances by reducing LUTs by 82.96% and slices by 74.28% than conventional XTEA method.
Keywords: cryptosystem; extended tiny encryption algorithm; Lorenz chaotic system; Verilog; Xilinx tool.
International Journal of Information and Computer Security, 2021 Vol.14 No.1, pp.3 - 19
Received: 15 Nov 2018
Accepted: 16 Mar 2019
Published online: 17 Dec 2020 *