Title: VLSI implementation of an efficient MBIST architecture using RLFSR

Authors: Omanakuttan Sheela Nisha; K. Siva Sankar

Addresses: Department of Computer Science and Engineering, Lourdes Matha College of Science and Technology, Trivandrum, Kerala, India ' Department of Information Technology, Nooral Islam University, Thuckalay, Tamil Nadu, India

Abstract: An area and power efficient FPGA implementation approach of memory built-in self-test (MBIST) is presented in this paper. It is consist of an array of 2-bit linear feedback shift register (LFSR), the switching activity of address generator used in previous MBIST architectures are high. This unwanted switching activity is affecting the power consumption of entire MBIST. We propose the MBIST with ring-based LFSR used to avoid the main problem of power consumption. The 2-bit 2N pattern generator combines with a conventional (N − 2) bit 2(N−2) LFSR and a 2-bit four pattern generator are both controlled separately by a two separate clocks of two different frequencies to generate all possible memory address location of a memory under test. The proposed architecture is implemented on vertex4 FPGA technology in Xilinx software. We showed that results improve the performance of the proposed design by comparing with the existing design.

Keywords: MBIST; RLFSR; 2D-LFSR; switching activity; FPGA; Xilinx.

DOI: 10.1504/IJSCC.2020.109076

International Journal of Systems, Control and Communications, 2020 Vol.11 No.3, pp.288 - 304

Accepted: 15 Jul 2019
Published online: 17 Aug 2020 *

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