Authors: João Gabriel Reis; Antônio Augusto Fröhlich
Addresses: Software/Hardware Integration Lab, Federal University of Santa Catarina, 88040-900 Florianópolis – SC, Brazil ' Software/Hardware Integration Lab, Federal University of Santa Catarina, 88040-900 Florianópolis – SC, Brazil
Abstract: Rigid partitioning of components in hardware/software co-design flows can lead to suboptimal choices in embedded systems with dynamic runtime requirements. FPGAs allow systems to cope with such unforeseen conditions by changing portions of hardware dynamically while other parts are still active. Nevertheless, to guarantee a transparent reconfiguration, it is necessary to ensure that it does not disrupt the timing requirements of the running tasks and vice-versa. This work proposes a deterministic FPGA reconfiguration mechanism capable of mitigating the interference generated by I/O operations occurring in parallel. The reconfiguration is confined in the idle time without interfering with or being interfered by other activities occurring in the system, including peripherals performing I/O. The scheme decomposes the reconfiguration process in small steps such that it is preemptable, and compliant with timing requirements. To quantify the impact of I/O interference on FPGA reconfiguration, we measured the execution time to load bitstreams from memory to the FPGA reconfiguration interface with multiple peripherals performing I/O in parallel. Results show that if the I/O interference is not taken into account and mitigated, the reconfiguration time can grow up to 8,800% when peripherals are performing I/O operations through DMA.
Keywords: field-programmable gate array; FPGA; dynamic reconfiguration; I/O interference; embedded systems; partial reconfiguration; power management; interference mitigation; speculative reconfiguration; operating system.
International Journal of Embedded Systems, 2020 Vol.13 No.2, pp.236 - 253
Received: 08 Jun 2018
Accepted: 02 Jun 2019
Published online: 05 Aug 2020 *