Title: Reconfigurable half-precision floating-point real/complex fused multiply and add unit

Authors: J. Jean Jenifer Nesam; S. Sivanantham

Addresses: School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, Tamil Nadu, India ' School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, Tamil Nadu, India

Abstract: Multiplication followed by an addition/subtraction is the common operation in many digital signal and image processing applications. This paper presents a reconfigurable floating-point real/complex fused multiply and add (R/C-FMA) unit using small precision (IEEE-754-2008 16-bit half-precision) format. The developed FMA can be reconfigurable from real to complex based on the control bits. This architecture performs real FMA [(a × b) + c], complex FMA {[(a + ib) × (c + id)] + (e + if)} or mixed real and complex FMA {[(a + ib) × (c + id)] + e}. The field programmable gate array (FPGA) implementation of R/C-FMA design, utilises the modern features of inbuilt DSP blocks for mantissa multiplication and addition/subtraction. The efficient DSP usage for fp16 FMA design shows a 60% reduction in LUT area when compared to conventional fp32 FMA.

Keywords: FMA architecture; floating-point arithmetic; half-precision; FFT processor; reconfigurable system.

DOI: 10.1504/IJMPT.2020.108488

International Journal of Materials and Product Technology, 2020 Vol.60 No.1, pp.58 - 72

Accepted: 18 Feb 2020
Published online: 07 Jul 2020 *

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