You can view the full text of this article for free using the link below.

Title: Controlled hardware architecture for fractal image compression

Authors: Hasanujjaman; Utpal Biswas; M.K. Naskar

Addresses: Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani-741235, India ' Department of Computer Science and Engineering, University of Kalyani, Kalyani, West Bengal, India ' Department of Electronics and Tele-Communication Engineering, Jadavpur University, Jadavpur, West Bengal, India

Abstract: Fractal image compression utilising algorithms have a high demand on the memory interface and the processor's arithmetic unit, which in turn fails to utilise the full capabilities of a general purpose processor. Since the algorithm is repetitive, the parallelisation reduces the time complexity of the otherwise expensive coding scheme. The design for FIC is proposed in this paper. It is based on the fact that the algorithm requires only integer arithmetic with repetitive use of the same data set. Making use of multiple functional units, controlled parallelism is introduced in this process. This makes encoding time 80 times faster than high level software implementation. It is 25 times faster than the assembly level implementation on a DSP processor.

Keywords: FIC; hardware architecture; iterated function systems; Verilog HDL.

DOI: 10.1504/IJNBM.2020.107415

International Journal of Nano and Biomaterials, 2020 Vol.9 No.1/2, pp.50 - 63

Received: 05 Sep 2019
Accepted: 18 Sep 2019

Published online: 26 May 2020 *

Full-text access for editors Access for subscribers Free access Comment on this article