Authors: Mohammad Samadi Gharajeh; Majid Haghparast
Addresses: Young Researchers and Elite Club, Tabriz Branch, Islamic Azad University, Tabriz, Iran ' Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran
Abstract: Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.
Keywords: register file; MIPS register file; decoder; multiplexer; reversible gate; reversible circuit design; quantum computing; reversible register file; reversible decoder; reversible multiplexer.
International Journal of High Performance Systems Architecture, 2020 Vol.9 No.1, pp.11 - 19
Received: 22 Aug 2019
Accepted: 14 Oct 2019
Published online: 01 May 2020 *