Authors: N. Sambamurthy; M. Kamaraju
Addresses: ECE Department, Gudlavalleru Engineering College, JNTUK, Gudlavalleru, India ' ECE Department, Gudlavalleru Engineering College, JNTUK, Gudlavalleru, India
Abstract: Nowadays, embedded video and image processing capabilities are much more demands with image quality. Digital image noise mostly occurs in a communication channel. The variety of random variation of white and black dots on the surface of an image, seriously degrading the image quality. Median filters are having the excellent image denoising processing capabilities. These filters are particularly reducing the salt-and-pepper noise and increase the throughput with less complexity. In contrast, power efficient remains an untapped area for improvement in the sorting-based network. For this, the filter is designed with hybrid sorting network with intelligent clock gating technique is also presented. The implementation of median filter on ARTIX-7 (90 nm) FPGA. The practical results shows the effectiveness of combined parallel and pipelined with clock gating architecture reduces the dynamic power and complexities in terms of FPGA resource usage and frequency.
Keywords: median filter; noise reduction; FPGA; parallel processing; pipeline technique; clock gating; sorting network.
International Journal of Digital Signals and Smart Systems, 2020 Vol.4 No.1/2/3, pp.80 - 86
Received: 21 Jan 2019
Accepted: 24 May 2019
Published online: 19 Mar 2020 *