Title: Parallel algorithms for robot path planning with simpler VLSI architecture

Authors: Michael Arock, R. Ponalagusamy

Addresses: Department of Computer Applications, National Institute of Technology, Tiruchirappalli 620 015, Tamilnadu, India. ' Department of Mathematics, National Institute of Technology, Tiruchirappalli 620 015, Tamilnadu, India

Abstract: This paper proposes a parallel algorithm for robot path planning on a linear array with a reconfigurable pipelined bus system (LARPBS) through the construction of a Voronoi diagram on a binary image of the workspace. The algorithm is based on a d4 distance metric, and it does not incur any additional time or processor requirements compared with those of a previously reported proposal (Tzionas et al., 1997). This paper recommends the same model as the simpler VLSI architecture for the problem in question.

Keywords: LARPBS; linear array; reconfigurable pipelined bus; parallel algorithms; robot path planning; Voronoi diagram; VLSI architecture.

DOI: 10.1504/IJCAT.2006.010600

International Journal of Computer Applications in Technology, 2006 Vol.26 No.3, pp.157 - 163

Published online: 07 Aug 2006 *

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