Title: CSL: FPGA implementation of lightweight block cipher for power-constrained devices

Authors: Hemraj Shobharam Lamkuche; Dhanya Pramod

Addresses: Symbiosis International (Deemed University), Pune, Maharashtra, India ' Symbiosis Centre for Information Technology (SCIT), Symbiosis International (Deemed University), Pune, Maharashtra, India

Abstract: The exploration of interconnected devices, embedded devices, sensors, and various network-connected devices helps to communicate each other and exchange communications. These devices overcome with security threats related to privacy and data exchange over billions of devices are interconnected. Lightweight block ciphers aim to provide a feasible solution for power-constrained devices which includes Radio-frequency identification (RFID) tags, ubiquitous computing, wireless sensor network, aggregation network and IoT. In this paper, we have implemented a lightweight block cipher compact, secure, and lightweight (CSL). It operates on 64-bit block size, and key size varies from 64-bit to 128-bit key for encryption and decryption. The hardware implementation of CSL algorithm was thrived using field programmable gate array (FPGA) architecture. A pipelined design of compact S-boxes implemented on Digilent Nexys 4 DDR Artix™-7 board. Our experimental results of CSL consumes 1145 LUTs (Lookup Tables) and has fewer memory requirements. CSL shows resistant against various cryptanalytic attacks.

Keywords: field programmable gate array; FPGA; lightweight block cipher; internet of things; IoT; Feistel structure; symmetric encryption; embedded devices; computer security; cryptanalytic attacks.

DOI: 10.1504/IJICS.2020.105185

International Journal of Information and Computer Security, 2020 Vol.12 No.2/3, pp.349 - 377

Received: 29 Nov 2017
Accepted: 13 Nov 2018
Published online: 14 Feb 2020 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article