Title: A real time implementation of interline dynamic voltage restorer for improvement of power quality

Authors: Ramchandra Nittala; Alivelu Manga Parimi

Addresses: Department of Electrical and Electronics Engineering, BITS Pilani Hyderabad Campus, Hyderabad, India ' Department of Electrical and Electronics Engineering, BITS Pilani Hyderabad Campus, Hyderabad, India

Abstract: Voltage deviations which occur frequently in the form of voltage sag/swell cause severe disturbances and damage sensitive loads present on the distribution side of power system. One of the feasible solutions to mitigate these voltage sags/swells is by utilising FACTS devices. The FACTS device proposed in this paper is interline dynamic voltage restorer (IDVR) which contains two or more dynamic voltage restorers (DVR) with a common DC link. In this paper, IDVR is designed for a specific application to mitigate power quality problems in an existing real time load. A case study of the load network data of BITS Pilani Hyderabad Campus in Telangana, India which is spread over 200 acres is considered as the real time load. Various multiple voltage sag/swell scenarios are analysed in the real time load. The results have proven that the IDVR can effectively mitigate multiple voltage sags/swells in the considered real time load.

Keywords: interline dynamic voltage restorer; IDVR; power quality; voltage source inverter; VSI; voltage sag/swell.

DOI: 10.1504/IJPELEC.2020.105147

International Journal of Power Electronics, 2020 Vol.11 No.2, pp.179 - 194

Received: 26 Jul 2017
Accepted: 28 Oct 2017

Published online: 14 Feb 2020 *

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