Title: Cascaded H-bridge inverter with reduced device count control considering harmonic distortion minimisation

Authors: Faouzi Armi; Lazhar Manai; Mongi Besbes

Addresses: Laboratory of Robotics, Informatics and Complex Systems (RISC), National Engineering School of Tunis, University of Tunis, El Manar, BP No. 37, Le Belvédère, 1002 Tunis, Tunisia; Higher Institute of Information and Communication Technologies, University of Carthage, BP No. 123-1164, Hammam Chatt, Tunisia ' Laboratory of Robotics, Informatics and Complex Systems (RISC), National Engineering School of Tunis, University of Tunis, El Manar, BP No. 37, Le Belvédère, 1002 Tunis, Tunisia; Higher Institute of Information and Communication Technologies, University of Carthage, BP No. 123-1164, Hammam Chatt, Tunisia ' Laboratory of Robotics, Informatics and Complex Systems (RISC), National Engineering School of Tunis, University of Tunis, El Manar, BP No. 37, Le Belvédère, 1002 Tunis, Tunisia; Higher Institute of Information and Communication Technologies, University of Carthage, BP No. 123-1164, Hammam Chatt, Tunisia

Abstract: In this paper, a serial/parallel cascaded H-bridge (CHB) multilevel inverter is presented. The topology has the advantage of reduced number of switching devices, DC-sources and gate driver circuits. Consequently, cost and complexity are greatly minimised, providing the same number of output voltage levels even more compared to conventional structures and other topologies given in some recent literatures in which authors have proposed new topologies with reduced circuit devices count (RDC). The main contribution of this work is the ability to choose a set of harmonic order to be eliminated; in other similar works, PWM technique is only capable to minimise total harmonic distortion (THD) without eliminating selected harmonic which require a complex output filter. The feasibility and effectiveness of the proposed topology is evaluated with intensive simulation study and experimentally tested on a prototype using a field-programmable gate array (FPGA) to implement N-R algorithm for inverter selective harmonic elimination (SHE) control.

Keywords: serial/parallel CHB multilevel inverter; reduced device count; Newton-Raphson algorithm; switching angles; selective harmonic elimination; SHE; total harmonic distortion; THD; field-programmable gate array; FPGA.

DOI: 10.1504/IJPELEC.2020.105145

International Journal of Power Electronics, 2020 Vol.11 No.2, pp.139 - 159

Received: 14 May 2017
Accepted: 14 Sep 2017
Published online: 14 Feb 2020 *

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