Authors: Debasis Mukherjee; B.V. Ramana Reddy
Addresses: Department of Electronics and Communication Engineering, School of Engineering, Sir Padampat Singhania University, Bhatewar, Udaipur, 313601, Rajasthan, India; University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, Sector 16C Dwarka, Delhi, 110078, India ' University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, Sector 16C Dwarka, Delhi, 110078, India
Abstract: Reduction of process cost is the key factor for profitability in any industry. Semiconductor industry is also not an exception of this rule. In this paper, a novel transistor structure has been proposed with reduced process cost and almost same functionality compared to conventional MOSFET transistor. Details fabrication steps of the novel transistor have been proposed. Working of the proposed structure resembles conventional MOSFET, but structure wise there are many differences. Necessity of source extension and drain extension has been uninvolved, resulting less fabrication cost and higher concentration of transistors in same chip area. Another improvement is removal of gate spacer, resulting cutting down of process cost. Both the conventional MOSFET and the proposed one have been simulated by Sentaurus TCAD toolkit for 7 nm technology generation. The performance of the proposed transistor has been found satisfactory compared to the conventional MOSFET as per the guidance given in International Technology Roadmap for Semiconductors or ITRS (2013) version.
Keywords: 7 nm; cost; CMOS; device level; fabrication; ITRS; MOSFET; process cost; production; profitability; TCAD; VLSI.
International Journal of Intelligent Enterprise, 2020 Vol.7 No.1/2/3, pp.291 - 305
Received: 26 Jul 2018
Accepted: 14 Jan 2019
Published online: 27 Jan 2020 *