Title: Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors
Authors: G. Dhanalakshmi; M. Sundarambal; K. Muralidharan
Addresses: Department of ECE, Ashoka Institute of Engineering and Technology, Hyderabad, Telangana, India ' Electrical and Electronics Engineering, Coimbatore Institute of Technology, Coimbatore, India ' Electrical and Electronics Engineering, Coimbatore Institute of Technology, Coimbatore, India
Abstract: In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.
Keywords: load/store queue; LQ/SQ; static power; dynamic power; CAM; SRAM.
International Journal of Advanced Intelligence Paradigms, 2020 Vol.15 No.1, pp.89 - 97
Received: 07 Jul 2016
Accepted: 01 Oct 2016
Published online: 14 Dec 2019 *