Title: Mathematical models and methods for functional control of large-scale integrated circuits at the stage of their production

Authors: K.K. Smirnov; A.V. Nazarov

Addresses: Scientific Research Institute of System Analysis (SRISA/NIISI RAS), Nakhimovsky Ave., 36, Building 1, 117218, Moscow, Russia ' Moscow Aviation Institute (National Research University), Volokolamskoe Ave., 4, GSP-3, 125993, Moscow 125080, Russia

Abstract: The paper proposes a hardware-software complex for generating functional tests for the equipment Advantest V93000, AEHR MAX3B, etc., working on the basis of the original software and the original language for the description of functional test algorithms. This language is based on the application programming language, and the hardware description language allows describing the logical circuit, the conclusions of the test device, the temporal characteristics of signals and state machines. The testing algorithm is described by instructions, similar to the high-level language such as STeeL. The combination of the hardware description language and the high-level programming language makes the development process of functional tests more flexible and understandable. Describing the interaction of functional blocks, the developer operates the instructions that describe conductors, finite state machines, signals, logic gates, and signal levels. When describing the algorithm, the developer operates the application instructions, variables, loops, functions, and conditions. From the point of view of the developer of the algorithm, work with the signals and circuit elements is comparable to a variable high-level programming language. The language allows working with designed tests, objects and IP blocks, developing own functional components allowing their re-use and developing cross-platform functional tests (tests that can be run in other hardware). The language allows combining different tests that test different interfaces in a single test with an opportunity for a parallel test and splitting functional tests into many tests in the case if the number of channels of the testing equipment is less than the number of signal pins. Moreover, there is a possibility to perform the post-processing of test tables with the opportunity to perform complex replacements or generate state signals depending on the state of the other. An important instrument for developing the environment is a debugger that allows improving the algorithms and analysing the status signals connected to the test chip. In addition, the developed IP blocks can be used for diagnostics and periodic certification of measuring equipment.

Keywords: integrated circuits; testing of integrated circuits; software; functional control; mathematical models.

DOI: 10.1504/IJNT.2019.102402

International Journal of Nanotechnology, 2019 Vol.16 No.1/2/3, pp.162 - 173

Published online: 12 Sep 2019 *

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