Title: An adaptive low power coding scheme for the NoC

Authors: M. Jasmin; T. Vigneswaran

Addresses: ECE Department, Bharath University, Tamil Nadu, India ' School of Electronics, VIT, Chennai Campus, Tamil Nadu, India

Abstract: Low power system design is important for system-on-chip design where communication takes place at higher data rate to realise the system functionality. Low power coding reduces energy by reducing self-switching activity or coupling switching activity. But under typical network-on-chip (NOC) system, we require a low power coding scheme to handle different kinds of data traffic from different IP core at different instant and different places in system-on-chip (SOC). As single low power coding scheme will not solve all application demands, a correlation analysis based adaptive data coding scheme is presented. Based on the classification of data traffic as low, moderate and highly correlated, different coding scheme is applied. The proposed system is simulated in labVIEW FPGA tool for the USRP RIO target. Based on comparative analysis of power consumption between the existing coding schemes and proposed adaptive scheme 25% energy saving is achieved at the worst case scenario.

Keywords: network-on-chip; NoC; system-on-chip; SoC; correlation analysis; USRP RIO.

DOI: 10.1504/IJAIP.2019.101982

International Journal of Advanced Intelligence Paradigms, 2019 Vol.13 No.3/4, pp.324 - 333

Received: 06 Jul 2016
Accepted: 07 Mar 2017
Published online: 03 Sep 2019 *

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