Title: MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation

Authors: Geeta Patil; Neethu Bal Mallya; Biju K. Raveendran

Addresses: Department of Computer Science and Information Systems, BITS, Pilani K.K. Birla Goa Campus, Goa, India ' Department of Computer Science and Information Systems, BITS, Pilani K.K. Birla Goa Campus, Goa, India ' Department of Computer Science and Information Systems, BITS, Pilani K.K. Birla Goa Campus, Goa, India

Abstract: This paper proposes a novel cache coherence protocol - MOESIF - to improve the off chip and on chip bandwidth usage. This is achieved by the reducing the number of write backs to the next level memory and by reducing the numbers of responders to a cache miss when multiple copies of data exists in private caches. Experimental evaluation of various splash-2 benchmark programs on the CACTI 5.3 and CACOSIM simulators reveals that the MOESIF protocol outperforms all other hardware based coherence protocols in terms of energy consumption and access time. MOESIF protocol on an average offers 94.62%, 88.94%, 88.88% and 4.47% energy saving, and 96.37%, 92.83%, 92.77% and 9.21% access time saving over MI, MESI, MESIF and MOESI protocol respectively for different numbers of cores/processors.

Keywords: cache coherence; MC/MP cache; energy-efficient coherence protocols.

DOI: 10.1504/IJES.2019.100866

International Journal of Embedded Systems, 2019 Vol.11 No.4, pp.493 - 507

Received: 11 Aug 2016
Accepted: 12 Jul 2017
Published online: 19 Jul 2019 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article