Title: DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems

Authors: Shubhangi K. Gawali; Biju K. Raveendran

Addresses: Department of Computer Science, BITS PILANI University, Goa, India ' Department of Computer Science, BITS PILANI University, Goa, India

Abstract: Optimising energy consumption has become the primary focus of research in recent years. Static and dynamic energy optimisation during task scheduling is one of the most prominent measures available. This is achieved mainly by shutdown and slowdown techniques. In uni-processor real-time systems, the most widely used shutdown and slowdown techniques are dynamic procrastination (DP) and dynamic voltage and frequency scaling (DVFS). This paper proposes DPVFS a hard real-time task scheduler for multi-core (MC) system to optimise overall energy consumption without deadline misses. DPVFS combines DP and DVFS for MC systems to save overall energy consumption. DPVFS shuts the processor down whenever possible with the help of procrastination. If shutdown is not possible, it adjusts the voltage and frequency to reduce dynamic energy consumption. The experimental evaluation of DPVFS with synthetically generated benchmark program suites shows savings of 18.8% and 33.2% of overall energy over DP based schedulers and DVFS based schedulers respectively.

Keywords: procrastination; dynamic voltage and frequency scaling; DVFS; multi-core real-time scheduling.

DOI: 10.1504/IJES.2019.100862

International Journal of Embedded Systems, 2019 Vol.11 No.4, pp.461 - 471

Received: 08 Oct 2016
Accepted: 06 Jun 2017

Published online: 25 Jun 2019 *

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