Title: A delay-fault feature based hardware Trojan detection method

Authors: Yan Feng; Ye Guo; Guanfei Gong; Xiaolin Tang; Jingrui Hu; Zhiqiang Li

Addresses: State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, No. 3 Beitucheng West Road, Chaoyang District, Beijing 100029, China ' Institute of Microelectronics, Chinese Academy of Sciences, No. 3 Beitucheng West Road, Chaoyang District, Beijing 100029, China ' Institute of Microelectronics, Chinese Academy of Sciences, No. 3 Beitucheng West Road, Chaoyang District, Beijing 100029, China ' State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, No. 3 Beitucheng West Road, Chaoyang District, Beijing 100029, China; University of Chinese Academy of Sciences, No. 1 Yanqihu East Road, Huairou District, Beijing 100049, China ' State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, No. 3 Beitucheng West Road, Chaoyang District, Beijing 100029, China; University of Chinese Academy of Sciences, No. 1 Yanqihu East Road, Huairou District, Beijing 100049, China ' State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, No. 3 Beitucheng West Road, Chaoyang District, Beijing 100029, China

Abstract: The globalisation of the semiconductor supply chain has created new challenges for security researchers. Hardware Trojans pose a critical threat to integrated circuit (IC) security, yet existing detection methods struggle with process variations and high-dimensional data. To significantly improve detection efficiency, this paper introduces a novel hardware Trojan detection approach achieving a 97.07% detection rate with 98.77% confidence while remaining resilient to ±5% process variations (PV). Firstly, the delay-fault features are extracted from the test responses obtained during the transition delay fault (TDF) pattern simulation. Subsequently, to improve the detection efficiency, the dimensionality of the features is reduced by employing the principal component analysis (PCA). Finally, the k-nearest neighbours (k-NN) algorithm is utilised to classify the test chips. Experimental results on RS232 benchmarks confirm its superior performance over traditional side-channel-based detection techniques, making it a practical and robust solution for hardware security in semiconductor manufacturing.

Keywords: hardware Trojan; delay-fault feature; transition delay fault; TDF; k-nearest neighbours; k-NN; principal component analysis; PCA.

DOI: 10.1504/IJSN.2025.146762

International Journal of Security and Networks, 2025 Vol.20 No.2, pp.110 - 121

Received: 24 Mar 2025
Accepted: 07 Apr 2025
Published online: 16 Jun 2025 *

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